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tonegen_design [2022/03/16 23:24] dpisuperadmin [Minimal Tone Generator with Volume Control] |
tonegen_design [2022/03/20 03:45] dpisuperadmin |
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==== Minimal Tone Generator with Volume Control ==== | ==== Minimal Tone Generator with Volume Control ==== | ||
- | A full synthesizer, as described below, | + | A full synthesizer may take more that its fair share of FPGA logic. |
The API for a simple tone generator might specify the musical note to play, the volume in the range of 0 to 100, and the number of milliseconds to play the note. We might also want to play a file of notes where each line the the file has the note, volume, and duration. | The API for a simple tone generator might specify the musical note to play, the volume in the range of 0 to 100, and the number of milliseconds to play the note. We might also want to play a file of notes where each line the the file has the note, volume, and duration. | ||
- | dpset tonegen | + | dpset tonegen |
- | dpset tonegen | + | dpset tonegen |
{{ wiki: | {{ wiki: | ||
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The minimum output of the 2R-R circuit is 0.013 and the maximum value is 0.9935, a ratio of low to high of about 76. While we have lost a great deal of resolution, we have gone from 4 bits of dynamic range for the linear R-2R network to over 6 bits of dynamic range using a 2R-R network. | The minimum output of the 2R-R circuit is 0.013 and the maximum value is 0.9935, a ratio of low to high of about 76. While we have lost a great deal of resolution, we have gone from 4 bits of dynamic range for the linear R-2R network to over 6 bits of dynamic range using a 2R-R network. | ||
- | What if we combined the linear pulse density modulation with the non-linear DAC? We could PDM control each of the FPGA output pins with a separate 4 bit counter. | + | {{ : |
Our design is now ready for a Verilog Wishbone implementation. | Our design is now ready for a Verilog Wishbone implementation. | ||
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an 8 bit duration set by the host, | an 8 bit duration set by the host, | ||
- | (The diagrams in this section were generated using Octave. | + | (The diagrams in this section were generated using Octave. |
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grid on; | grid on; | ||
print -dpng '/ | print -dpng '/ | ||
- | |||
- | % Generate 100 points on an log curve and map the gain | ||
- | % to setting in pwm - nonlinear DAC scheme. | ||
- | % the actual table to use in the API driver modules. | ||
- | % Manually add {0,0,0,0} and {15, | ||
- | |||
- | % Get the target gains | ||
- | x = 1:1:100; | ||
- | out = exp((5 .* x) ./ 100) ./ 150; | ||
- | target_idx = 1; | ||
- | % loop past all possible gains recording the first to pass out(target_idx) | ||
- | idx = 0; | ||
- | for i3 = 0:15; | ||
- | for i2 = 0:15; | ||
- | for i1 = 0:15; | ||
- | for i0 = 0:15; | ||
- | idx = idx +1; | ||
- | | ||
- | if outval > out(target_idx), | ||
- | | ||
- | | ||
- | | ||
- | end | ||
- | end | ||
- | end | ||
- | end | ||
- | end | ||
*/ | */ |