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usersguide:usersguide [2022/02/25 07:32] dpisuperadmin |
usersguide:usersguide [2022/03/12 23:13] (current) dpisuperadmin [Software Defined Peripherals on the Baseboard4] |
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The Baseboard connects to your computer using a USB-serial link. Data over the link consists of packets of binary data that read and write the registers in the software defined peripherals in DPCore. | The Baseboard connects to your computer using a USB-serial link. Data over the link consists of packets of binary data that read and write the registers in the software defined peripherals in DPCore. | ||
You can download and install dpdaemon with the following commands: | You can download and install dpdaemon with the following commands: | ||
- | | + | |
- | cd dpdaemon | + | cd dpdaemon |
- | make | + | make |
- | sudo make install | + | sudo make install |
- | The Baseboard has an FTDI USB-to-serial interface. | + | The Baseboard has an FTDI USB-to-serial interface. |
- | dpdaemon -l / | + | sudo addgroup $LOGNAME dialout |
+ | | ||
- | You can perform a quick test that everything is working by changing the LEDs on the Baseboard with the command: | + | You can perform a quick test that everything is working by changing the LEDs on the Baseboard with the commands: |
- | / | + | |
+ | | ||
Dpdaemon is a true daemon in that, by default, it will disassociate from the controlling terminal, respawn itself, and use syslog() to report errors. | Dpdaemon is a true daemon in that, by default, it will disassociate from the controlling terminal, respawn itself, and use syslog() to report errors. | ||
Line 181: | Line 183: | ||
sys.exit() | sys.exit() | ||
| | ||
- | |||
- | ==== Build a Robot Using a Baseboard4 ==== | ||
- | ==== Use ROS2 to Control Your Robot ==== | ||
- | ==== How to Write a Custom Driver for dpdaemon ==== | ||
- | ==== How to Write a Verilog Peripheral ==== | ||
- | In this section you will see how to use Verilog to build FPGA applications. | ||
- | * "hello world" in Verilog | ||
- | * use iverilog to test your Verilog circuit | ||
- | * install the Xilinx compiler | ||
- | * compile your design and test it on the Baseboard | ||
- | |||
- | === "Hello World" in Verilog === | ||
- | //(Bob: put nice introductory text here)// | ||
- | |||
- | Save the following as counter.v | ||
- | // Simple up counter for the Baseboard. | ||
- | // Visible update rate is about 12 times per second | ||
- | | ||
- | module counter(CK12, | ||
- | input | ||
- | output | ||
- | | ||
- | reg [27:0] count; | ||
- | | ||
- | initial | ||
- | begin | ||
- | count = 0; | ||
- | end | ||
- | | ||
- | always @(posedge CK12) | ||
- | begin | ||
- | count <= count + 28'b1; | ||
- | end | ||
- | | ||
- | assign LEDS = count[27: | ||
- | | ||
- | endmodule | ||
- | |||
- | //Bob: do a code review of the above and be sure to describe wire, reg, assign and "< | ||
- | |||
- | |||
- | === Test you Verilog design using iverilog === | ||
- | //Bob: describe why you'd want to do simulation// | ||
- | |||
- | Install iverilog and gtkwave on a Debian system with the command: | ||
- | sudo apt-get install iverilog gtkwave | ||
- | |||
- | //Bob: describe how a test bench works in iverilog// | ||
- | |||
- | Save the following as counter_tb.v | ||
- | // iverilog test bench for the simple counter in counter.v | ||
- | | ||
- | `timescale 10ns/10ns | ||
- | | ||
- | module counter_tb; | ||
- | // direction is relative to the DUT | ||
- | reg clk; // 12.5 MHz system clock | ||
- | wire [7:0] leds; // LEDs on Baseboard | ||
- | | ||
- | // Add the device under test | ||
- | counter counter_dut(clk, | ||
- | | ||
- | // generate the clock | ||
- | initial | ||
- | always | ||
- | | ||
- | initial | ||
- | begin | ||
- | $dumpfile (" | ||
- | $dumpvars (0, counter_tb); | ||
- | | ||
- | // 100 million steps of 10ns is one tenth of a second | ||
- | #100000000 | ||
- | $finish; | ||
- | end | ||
- | endmodule | ||
- | |||
- | Run the simulation, convert the output to a gtkwave format, and display the results with the commands: | ||
- | iverilog -o counter_tb.vvp counter_tb.v counter.v | ||
- | vvp counter_tb.vvp -lxt2 | ||
- | gtkwave counter_tb.xt2 | ||
- | |||
- | To view the LED waveforms click on " | ||
- | {{ : | ||
- | |||
- | === Install and Test the Xilinx Toolchain === | ||
- | Once your simulation output is correct you are ready to compile and download your design to the FPGA. | ||
- | This section describes how to install the Xilinx FPGA design tools, how to use the Xilinx command line tools to compile a Verilog design, and how to download the compiled code to the Baseboard. | ||
- | |||
- | The Baseboard uses a Xilinx Spartan-3E and a USB interface for both downloads and a host interface. | ||
- | |||
- | Xilinx provides a set of free design tools, ISE, which are part of their WebPACK download. | ||
- | |||
- | Start by going to the Xilinx download site at: http:// | ||
- | |||
- | Install the software by untarring the download file and running the " | ||
- | |||
- | The installation will ask which products to install. | ||
- | |||
- | Once the installation is complete you can add the Xilinx Verilog compiler toolchain to you path and verify that it can be found with the commands: | ||
- | export PATH=$PATH:/ | ||
- | which ise | ||
- | |||
- | By default, ise opens a graphical integrated development environment. | ||
- | |||
- | Before compiling your Verilog to an FPGA binary you need to tell the compiler how the wires in the Verilog module map to the physical FPGA pins. Xilinx uses a "user constraints file" (.ucf) for this. The minimum UCF file for your counter is shown below. | ||
- | NET " | ||
- | NET " | ||
- | NET " | ||
- | NET " | ||
- | NET " | ||
- | NET " | ||
- | NET " | ||
- | NET " | ||
- | NET " | ||
- | |||
- | The commands that Xilinx uses to compile Verilog for a SPartan3 can be hidden by a Makefile but you might be interested in the steps involved. | ||
- | |||
- | The first command, xst, synthesizes the Verilog file into a hardware design that is saved as a netlist file with an .ngc extension. | ||
- | echo "run -ifn counter.v -ifmt Verilog -ofn counter.ngc -p xc3s100e-4-vq100" | ||
- | |||
- | You have to specify the input file, the input file format, the name of the output file and the exact type of FPGA. Xst generates several report files and directories, | ||
- | |||
- | The ngdbuild command further decomposes the design into FPGA native elements such as flip-flops, gates, and RAM blocks. | ||
- | |||
- | ngdbuild | ||
- | |||
- | It is the ngdbuild command that first considers the pin location, loading, and timing requirements specified in the user constraints file, counter.ucf. | ||
- | |||
- | The Xilinx map command converts the generic elements from the step above to the elements specific to the target FPGA. It also performs a design rules check on the overall design. The map command produces two files, a Physical Constraints File file and a Native Circuit Description file, that are used in subsequent commands. | ||
- | |||
- | map -detail -pr b counter.ngd | ||
- | |||
- | The map command produces quite a few reports. | ||
- | |||
- | The place and route command (par) uses the Physical Constraints File and the Native Circuit Description to produce another Native Circuit Description file which contains the fully routed FPGA design. | ||
- | |||
- | par counter.ncd parout.ncd counter.pcf | ||
- | |||
- | Output processing starts with the bitgen program which converts the fully routed FPGA design into the pattern of configuration bits found in the FPGA after download. | ||
- | |||
- | bitgen -g StartUpClk: | ||
- | |||
- | The bitgen program lets you specify which clock pin to use during initialization and whether or not to generate a CRC checksum on the download image. | ||
- | |||
- | promgen -w -p bin -o counter.bin -u 0 counter.bit | ||
- | |||
- | The promgen program is a utility that converts bitstream files into various PROM file formats. | ||
- | |||
- | All of the commands described above, including xst, ngdbuild, map, par, bitgen, and promgen have excellent PDF manuals in either the ISE/ | ||
- | |||
- | echo "run -ifn counter.v -ifmt Verilog -ofn counter.ngc -p xc3s100e-4-vq100" | ||
- | ngdbuild | ||
- | map -detail -pr b counter.ngd | ||
- | par counter.ncd parout.ncd counter.pcf | ||
- | bitgen -g StartUpClk: | ||
- | promgen -w -p bin -o counter.bin -u 0 counter.bit | ||
- | |||
- | When the Baseboard powers up or after pressing the reset button the FPGA waits for an binary image from the serial port. Linux serial port drivers can suppress certain characters from an output stream. | ||
- | sudo stty --file=/ | ||
- | |||
- | Press the reset button and send the FPGA binary to the Baseboard with the command: | ||
- | cat counter.bin > /dev/ttyUSB | ||
- | |||
- | If all has gone well you should see an up counter on the Baseboard LEDs. | ||
- | |||
- | |||
- | ==== How to Write a Wishbone Peripheral ==== | ||
- | In this section you will see how to build your own custom Verilog peripheral. | ||
- | * the DPcore Wishbone bus | ||
- | * build a Verilog peripheral for DPcore | ||
- | * fold your peripheral in the DPcore build system. | ||
- | |||
- | === The Wishbone Bus === | ||
- | A Wishbone Bus is a synchronous, | ||
- | |||
- | In the case of DPcore, the Wishbone bus does not connect to a CPU but to an interface to a host computer. | ||
- | |||
- | {{ : | ||
- | |||
- | Wishbone supports different peripherals/ | ||
- | |||
- | Wishbone gives a general description of a peripheral bus. For example, Wishbone buses can be 8, 16, 32, or 64 bits wide. It is up the the implementer to decide things like bus width, clock frequencies, | ||
- | |||
- | {{ : | ||
- | |||
- | The diagram to the right shows the topology for PDcore. | ||
- | |||
- | |||
- | The paragraphs below describe the Wishbone bus as implemented for DPcore. | ||
- | |||
- | Peripheral Signal Names : | ||
- | CLK_I : System clock. | ||
- | |||
- | WE_I : Write enable. | ||
- | |||
- | STB_I : Strobe. | ||
- | |||
- | TGA_I : Address tag. A bus cycle with TGA_I set is a normal register read/ | ||
- | |||
- | ADR_I : Address. | ||
- | |||
- | STALL_O : Stalled. | ||
- | |||
- | ACK_O : Acknowledge. | ||
- | |||
- | DAT_X : An 8 bit data bus that is passed in ring from the bus controller through all peripherals and back to the bus controller. | ||
- | The "Port Size" is 8 bits and the " | ||
- | During a bus write cycle the peripheral latches DAT_I into the selected register. During a read bus cycle the peripheral ignore DAT_I and places the requested data on DAT_O. | ||
- | |||
- | The Verilog code fragment below shows a typical peripheral interface definition. | ||
- | |||
- | module dp_peri(CLK_I, | ||
- | input CLK_I; | ||
- | input WE_I; // direction. Read-from-peri==0; | ||
- | input TGA_I; | ||
- | input STB_I; | ||
- | input [7:0] ADR_I; | ||
- | output STALL_O; | ||
- | output ACK_O; | ||
- | input [7:0] DAT_I; | ||
- | output [7:0] DAT_O; | ||
- | input [7:0] clocks; | ||
- | inout [3:0] pins; // FPGA pins for this peripheral | ||
- | |||
- | |||
- | The DPcore implementation of Wishbone is fairly bare-bones. | ||
- | |||
- | |||
- | |||
- | === Download, Build, and Test DPcore === | ||
- | |||
- | |||
- | You can download the source code for DPcore and build a binary image with the following commands: | ||
- | git clone https:// | ||
- | cd DPCore/src | ||
- | # Edit perilist to set the peripherals in your build | ||
- | vi perilist | ||
- | make | ||
- | Expect several warnings about signals without loads. | ||
- | |||
- | sudo cp DPCore.bin / | ||
- | # start dpdaemon and test Baseboard LEDs | ||
- | dpdaemon -l / | ||
- | / | ||
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