Demand Peripherals

This page is a collection of design notes for the tone generator peripheral. The notes are not in any particular order but the last section is always about current design problems and next steps.

A common digital technique to generate very specific frequencies is to use what is called phase accumulation. The idea of a phase accumulator is to add a fraction of a cycle to the phase on each clock edge such that the accumulated phase reaches one (one full cycle) at the right time.

Let's use an example that is specific to this design. Let's say our audio update rate is 100 KHz. This gives use 10 microseconds per audio sample to the output DAC. The note C0 is 16.35 Hertz. In one sample a C0 note will change its phase by

  (16.35 / 100000) = 0.0001635 cycle

This is 0.000000000000101010110111 as a binary fraction, and this is what we would add to the accumulator every 10 microseconds to get 16.35 Hz output. Showing the phase offset as binary helps get across the idea that a hundredth of a cycle at 16.35 Hertz needs 24 bits of precision.

The FPGA never sees the note C0 or the frequency. All it sees is the phase offset per sample and this is set by a look-up table in the host. Feeding the MSB of the phase accumulator to an output pin is a minimal tone generator.

A full synthesizer, as described below, may take more that its fair share of FPGA logic. This is fine if the goal of the project is a synthesizer but is not fine if the user wants something that just beeps. This section describes something that beeps and has volume control.

The API for this might specify the musical note to play, the volume in the range of 0 to 100, and the number of milliseconds to play the note. For example: dpset tonegen tone b4 30 200

Square waves are easy to generate and have a pleasing sound since they have lots of higher harmonics. A more difficult question for a simple tone generator is how to control the volume. Human hearing perceives audio volume on a logarithmic scale. Electronics manufactures use what is called a 'audio taper' for potentiometers in audio applications. The diagram to the right shows an audio taper and we want our gain control to follow the same curve.

In this section the term 'gain' mean Vout/Vin where Vin the output voltage of the FPGA. Gain in this section is always between 0 and 1, and a lower gain means a lower volume.

There are two ways we can control the output volume of a square wave. The first is called 'pulse density modulation'. The idea that we turn off the output briefly during the high part of the square wave. By briefly we mean fast enough that an RC low pass filter can easily average the fast pulses into a DC level during the high time of the square wave. In our case, we have two simple approaches to pulse density modulation. One is to have, say, a 4 bit counter run continuously at a high rate and to turn off the output if the count is less than a target (volume) value. The output volume is N/16 where N is a 4 bit value set by the host. This give a linear volume relative to N.

The other PDM method we can use is to output one pulse every N clock cycles. This gives a 1/N kind of response. Both linear and reciprocal approaches have about the same minimum and maximum attenuation and differ mostly in the intermediate values.

The other approach to volume control is to build a DAC out of resistors connected to the four FPGA pins dedicated to the peripheral. Many DACs use what is called an 'R-2R' resistor network of give a linear response to the input values. (See https://en.wikipedia.org/wiki/Resistor_ladder#R-2R) We specifically do not want a linear response. We want one in which the higher values are much greater than their linear equivalents. Shown below is a circuit that does this. In it we swap the normal linear R-2R network resistors to get a 2R-R resistor network. The gain of the circuit is clearly non linear.

The minimum output of the 2R-R circuit is 0.013 and the maximum value is 0.9935, a ratio of low to high of about 76. While we have lost a great deal of resolution, we have gone from 4 bits of dynamic range for the linear R-2R network to over 6 bits of dynamic range using a 2R-R network.

What if we combined the linear pulse density modulation with the non-linear DAC? We could PDM control each of the FPGA output pins with a separate 4 bit counter. Doing this gives 64K possible gain setting but since some combinations give the same gain there are only 14000 unique gain settings. The minimum (one-sixteenth of the LSB) has a gain of 0.000817 and the maximum (all bits high) has a gain of 0.9314, giving us a dynamic range (log2(max/min)) of about 10 bits.

Our design now has

• a 24 bit phase accumulator,
• a 24 bit phase offset set by the host,
• four 4 bit PDM counter,
• four 4 bit gain settings set by the host,
• an 8 bit duration counter (to count milliseconds), and
• an 8 bit duration set by the host

A wave table captures a waveform by dividing it into slices and recording the output value for each slice. If the address decoder has N bits then the length of the table is 2^N. A wave table is usually driven by the N high bits of a phase accumulator.

The number of bits in each word determine the audio fidelity of the output. The values in the table are often the sign and the log of the desired value. Human hearing is such that perceived volume follows a logarithmic scale, and using log value makes subsequent gain and modulations easier since multiplication in a linear scale is just addition in a log scale. You can get the best fidelity from the least number of bits by making the waveform span the full range of M bits. The log function can be log-base-2, natural logarithm, or one of the standard u-law or a-law functions.

There are often more than one wave table and while each may have a default, all can be set from the host. The API is to be determined but might appear something like:

  dpset tonegen table_id 3      # select the table to download
  dpset tonegen table_addr 0    # point to first address in table
  dpset tonegen table_val 00 12 34 56 78 9a 87 56 78 88 99 aa bb cc dd ee
  dpset tonegen table_val ff ee ff ee ff ee ff ee ff ee ff ee ff ee ff ee
  (... for all 2^N values ...)

As mentioned above, gain is just addition when using log amplitude values. You have a few choices when dealing with the issue of overflow. One approach is to increase the sample size at each addition. This is shown in the diagram at the right. This approach maintains the greatest fidelity through the system at the expense of consuming more FPGA fabric. Another approach is to use saturating arithmetic. Saturating addition prevent overflow by clipping the output to a maximum value. For example, in 8 bits the value of FF+1 would not be zero but remain at FF.

Another consideration is the meaning of gain. If the values in the wave tables represent the smallest signal then gain means amplification. It the value represent the loudest samples possible then gain means attenuation and the gain block is actually subtraction.