This shows you the differences between two versions of the page.
Both sides previous revision Previous revision Next revision | Previous revision Next revision Both sides next revision | ||
usersguide:usersguide [2022/02/24 20:29] dpisuperadmin [How to Write a Custom Peripheral API] |
usersguide:usersguide [2022/02/28 00:48] dpisuperadmin |
||
---|---|---|---|
Line 182: | Line 182: | ||
| | ||
- | ==== Build a Robot Using a Baseboard4 | + | |
- | ==== Use ROS2 to Control | + | ==== A Brief Introduction to Verilog ==== |
- | ==== How to Write a Custom Driver | + | In this section you will see how to use Verilog to build FPGA applications. The purpose of this section is to give non-Verilog users a sense of how Verilog works. |
- | ==== How to Write a Verilog | + | * "hello world" in Verilog |
- | In this section you will see how to build your own custom Verilog peripheral. | + | * use iverilog to test your Verilog circuit |
+ | * install the Xilinx compiler | ||
+ | * compile your design and test it on the Baseboard | ||
+ | |||
+ | === "Hello World" in Verilog === | ||
+ | Most programming languages have a sample application that prints the phrase " | ||
+ | // Simple up counter for the Baseboard. | ||
+ | // Visible update rate is about 12 times per second | ||
+ | |||
+ | module counter(CK12, | ||
+ | input | ||
+ | output | ||
+ | |||
+ | reg [27:0] count; | ||
+ | |||
+ | initial | ||
+ | begin | ||
+ | count = 0; | ||
+ | end | ||
+ | |||
+ | always @(posedge CK12) | ||
+ | begin | ||
+ | count <= count + 28' | ||
+ | end | ||
+ | |||
+ | assign LEDS = count[27: | ||
+ | |||
+ | endmodule | ||
+ | |||
+ | Have you ever seen a circuit board with gold or copper fingers for the connector? | ||
+ | module counter(CK12, | ||
+ | input | ||
+ | output | ||
+ | Think of this counter module as a circuit board with nine signal pins on its edge. Clearly the code inside the module describes the digital circuitry on the imaginary circuit board. | ||
+ | |||
+ | You already know that a register is just an array of flip-flops. | ||
+ | reg [27:0] count; | ||
+ | |||
+ | You can tell the Verilog compiler what values to place in registers when the FPGA is loaded. | ||
+ | initial | ||
+ | begin | ||
+ | count = 0; | ||
+ | end | ||
+ | |||
+ | Consider a flip-flop. | ||
+ | always @(posedge CK12) | ||
+ | begin | ||
+ | count <= count + 28' | ||
+ | end | ||
+ | The left hand side is the input to the count register and the right hand side is the output of count plus one. The output of an edge-triggered flip-flop is given a value only on the edge of its input clock. | ||
+ | |||
+ | Assignment outside of a synchronous block is done with just an equal sign. This is called a // | ||
+ | assign LEDS = count[27: | ||
+ | sets the value of LEDS to the high eight bits of the counter. Just as you should not drive a wire with two different output, so Verilog wants just one output driving a wire or input. | ||
+ | assign outputA = inputX; | ||
+ | assign outputA = count + 1; | ||
+ | |||
+ | If you have understood this section you may want to get more information one of the many books and on-line tutorials on Verilog. | ||
+ | While the compiler can flag many errors it can not identify logic errors in your design. | ||
+ | |||
+ | === Test Your Verilog Design Using Iverilog | ||
+ | The word " | ||
+ | |||
+ | The simulation environment for a circuit is called a //test bench// | ||
+ | |||
+ | Install iverilog and gtkwave on a Debian system with the command: | ||
+ | sudo apt-get install iverilog gtkwave | ||
+ | |||
+ | Save the following as counter_tb.v | ||
+ | // iverilog test bench for the simple counter in counter.v | ||
+ | |||
+ | `timescale 10ns/10ns | ||
+ | |||
+ | module counter_tb; | ||
+ | // direction is relative to the DUT | ||
+ | reg clk; // 12.5 MHz system clock | ||
+ | wire [7:0] leds; // LEDs on Baseboard | ||
+ | |||
+ | // Add the device under test | ||
+ | counter counter_dut(clk, | ||
+ | |||
+ | // generate the clock | ||
+ | initial | ||
+ | | ||
+ | |||
+ | initial | ||
+ | begin | ||
+ | $dumpfile (" | ||
+ | $dumpvars (0, counter_tb); | ||
+ | |||
+ | // 100 million steps of 10ns is one second | ||
+ | # | ||
+ | $finish; | ||
+ | end | ||
+ | endmodule | ||
+ | |||
+ | Run the simulation, convert the output to a gtkwave format, and display the results with the commands: | ||
+ | iverilog -o counter_tb.vvp counter_tb.v counter.v | ||
+ | vvp counter_tb.vvp -lxt2 | ||
+ | gtkwave counter_tb.xt2 | ||
+ | |||
+ | To view the LED waveforms click on " | ||
+ | {{ : | ||
+ | |||
+ | === Install and Test the Xilinx Toolchain === | ||
+ | Once your simulation output is correct you are ready to compile and download your design to the FPGA. | ||
+ | This section describes how to install the Xilinx FPGA design tools, how to use the Xilinx command line tools to compile | ||
+ | |||
+ | The Baseboard uses a Xilinx Spartan-3E and a USB interface | ||
+ | |||
+ | Xilinx provides a set of free design tools, ISE, which are part of their WebPACK download. | ||
+ | |||
+ | Start by going to the Xilinx download site at: http:// | ||
+ | |||
+ | Install the software by untarring the download file and running the " | ||
+ | |||
+ | The installation will ask which products to install. | ||
+ | |||
+ | Once the installation is complete you can add the Xilinx Verilog compiler toolchain to you path and verify that it can be found with the commands: | ||
+ | export PATH=$PATH:/ | ||
+ | which ise | ||
+ | |||
+ | By default, ise opens a graphical integrated development environment. | ||
+ | |||
+ | Before compiling your Verilog to an FPGA binary you need to tell the compiler how the wires in the Verilog module map to the physical FPGA pins. Xilinx uses a "user constraints file" (.ucf) for this. The minimum UCF file for your counter is shown below. | ||
+ | NET " | ||
+ | NET " | ||
+ | NET " | ||
+ | NET " | ||
+ | NET " | ||
+ | NET " | ||
+ | NET " | ||
+ | NET " | ||
+ | NET " | ||
+ | |||
+ | The commands that Xilinx uses to compile Verilog for a SPartan3 can be hidden by a Makefile but you might be interested in the steps involved. | ||
+ | |||
+ | The first command, xst, synthesizes the Verilog file into a hardware design that is saved as a netlist file with an .ngc extension. | ||
+ | echo "run -ifn counter.v -ifmt Verilog -ofn counter.ngc -p xc3s100e-4-vq100" | ||
+ | |||
+ | You have to specify the input file, the input file format, the name of the output file and the exact type of FPGA. Xst generates several report files and directories, | ||
+ | |||
+ | The ngdbuild command further decomposes the design into FPGA native elements such as flip-flops, gates, and RAM blocks. | ||
+ | |||
+ | ngdbuild | ||
+ | |||
+ | It is the ngdbuild command that first considers the pin location, loading, and timing requirements specified in the user constraints file, counter.ucf. | ||
+ | |||
+ | The Xilinx map command converts the generic elements from the step above to the elements specific to the target FPGA. It also performs a design rules check on the overall design. The map command produces two files, a Physical Constraints File file and a Native Circuit Description file, that are used in subsequent commands. | ||
+ | |||
+ | map -detail -pr b counter.ngd | ||
+ | |||
+ | The map command produces quite a few reports. | ||
+ | |||
+ | The place and route command (par) uses the Physical Constraints File and the Native Circuit Description to produce another Native Circuit Description file which contains the fully routed FPGA design. | ||
+ | |||
+ | par counter.ncd parout.ncd counter.pcf | ||
+ | |||
+ | Output processing starts with the bitgen program which converts the fully routed FPGA design into the pattern of configuration bits found in the FPGA after download. | ||
+ | |||
+ | bitgen -g StartUpClk: | ||
+ | |||
+ | The bitgen program lets you specify which clock pin to use during initialization and whether or not to generate a CRC checksum on the download image. | ||
+ | |||
+ | promgen -w -p bin -o counter.bin -u 0 counter.bit | ||
+ | |||
+ | The promgen program is a utility that converts bitstream files into various PROM file formats. | ||
+ | |||
+ | All of the commands described above, including xst, ngdbuild, map, par, bitgen, and promgen have excellent PDF manuals in either the ISE/ | ||
+ | |||
+ | echo "run -ifn counter.v -ifmt Verilog -ofn counter.ngc -p xc3s100e-4-vq100" | ||
+ | ngdbuild | ||
+ | map -detail -pr b counter.ngd | ||
+ | par counter.ncd parout.ncd counter.pcf | ||
+ | bitgen -g StartUpClk: | ||
+ | promgen -w -p bin -o counter.bin -u 0 counter.bit | ||
+ | |||
+ | When the Baseboard powers up or after pressing the reset button the FPGA waits for an binary image from the serial port. Linux serial port drivers can suppress certain characters from an output stream. | ||
+ | sudo stty --file=/ | ||
+ | |||
+ | Press the reset button and send the FPGA binary to the Baseboard with the command: | ||
+ | cat counter.bin > / | ||
+ | |||
+ | If all has gone well you should see an up counter on the Baseboard LEDs. | ||
+ | |||
+ | |||
+ | ==== How to Write a Wishbone | ||
+ | In this section you will see how to build your own custom Verilog peripheral. | ||
* the DPcore Wishbone bus | * the DPcore Wishbone bus | ||
* build a Verilog peripheral for DPcore | * build a Verilog peripheral for DPcore | ||
- | * test your design using iverilog | ||
- | * install and test the Verilog toolchain | ||
* fold your peripheral in the DPcore build system. | * fold your peripheral in the DPcore build system. | ||
Line 248: | Line 433: | ||
The DPcore implementation of Wishbone is fairly bare-bones. | The DPcore implementation of Wishbone is fairly bare-bones. | ||
- | |||
- | === Install and Test the Xilinx Toolchain === | ||
- | In this section you'll see how to install the Xilinx FPGA design tools, how to use the Xilinx command line tools to compile a Verilog design, how to download the compiled code to the Baseboard, and how to automate the whole process using a Makefile. | ||
- | |||
- | The Baseboard uses a Xilinx Spartan-3E and a USB interface for both downloads and a host interface. | ||
- | |||
- | Xilinx provides a set of free design tools, ISE, which are part of their WebPACK download. | ||
- | |||
- | Start by going to the Xilinx download site at: http:// | ||
- | |||
- | Install the software by untarring the download file and running the " | ||
- | |||
- | The installation will ask which products to install. | ||
- | |||
- | Once the installation is complete you can add the Xilinx Verilog compiler toolchain to you path and verify that it can be found with the commands: | ||
- | | ||
- | which ise | ||
=== Download, Build, and Test DPcore === | === Download, Build, and Test DPcore === | ||
- | By default, ise opens a graphical integrated development environment. | ||
- | |||
- | The commands that Xilinx uses to compile Verilog for a SPartan3 are hidden by the Makefile but you might be interested in the steps involved. | ||
- | |||
- | The first command, xst, synthesizes the Verilog file into a hardware design that is saved as a netlist file with an .ngc extension. | ||
- | echo "run -ifn includes.v -ifmt Verilog -ofn DPcore.ngc -p xc3s100e-4-vq100" | ||
- | |||
- | You have to specify the input file, the input file format, the name of the output file and the exact type of FPGA. Xst generates several report files and directories, | ||
- | |||
- | The ngdbuild command further decomposes the design into FPGA native elements such as flip-flops, gates, and RAM blocks. | ||
- | |||
- | | ||
- | |||
- | It is the ngdbuild command that first considers the pin location, loading, and timing requirements specified in the user constraints file, baseboard3.ucf. | ||
- | |||
- | The Xilinx map command converts the generic elements from the step above to the elements specific to the target FPGA. It also performs a design rules check on the overall design. The map command produces two files, a Physical Constraints File file and a Native Circuit Description file, that are used in subsequent commands. | ||
- | |||
- | map -k 6 -detail -pr b DPcore.ngd | ||
- | |||
- | The map command produces quite a few reports. | ||
- | |||
- | The place and route command (par) uses the Physical Constraints File and the Native Circuit Description to produce another Native Circuit Description file which contains the fully routed FPGA design. | ||
- | |||
- | par DPcore.ncd parout.ncd DPcore.pcf | ||
- | |||
- | Output processing starts with the bitgen program which converts the fully routed FPGA design into the pattern of configuration bits found in the FPGA after download. | ||
- | |||
- | bitgen -g StartUpClk: | ||
- | |||
- | The bitgen program lets you specify which clock pin to use during initialization and whether or not to generate a CRC checksum on the download image. | ||
- | |||
- | promgen -w -p bin -o DPcore.bin -u 0 DPcore.bit | ||
- | |||
- | The promgen program is a utility that converts bitstream files into various PROM file formats. | ||
- | |||
- | All of the commands described above, including xst, ngdbuild, map, par, bitgen, and promgen have excellent PDF manuals in either the ISE/ | ||
Line 327: | Line 459: | ||
- | + | ==== Sections under development ==== | |
+ | * Build a Robot Using a Baseboard4 | ||
+ | * Use ROS2 to Control Your Robot | ||
+ | * How to Write a Custom Driver for dpdaemon | ||